There is an ever-present need and desire to reduce the size, weight and cost of electronic devices we use without sacrificing performance. A wide range of devices from displays, electronics, sensors and optical components, to name just a few, would benefit from methodologies that would produce ruggedized, lightweight, portable, small form factor, less power hungry and lower cost devices. Furthermore, new and novel markets and opportunities could be addressed and opened up if these devices could be made physically flexible and/or conformal.
To address these needs, previous approaches attempted to realize these devices by developing new, novel and expensive technologies. They have attempted to tailor the manufacturing process parameters such that flexible substrates polymer/plastic foil and metal foils may be used. However, polymers/plastics severely limit the maximum temperature a substrate may be exposed to during manufacturing. Metal foils, albeit immune from this temperature limit, suffer from a multitude of other problems that diminish device performance. This tailoring of manufacturing process parameters to suit the choice of substrate selection rather than device performance has resulted in less than ideal devices.
In addition to the desire to satisfy the needs just discussed, silicon on insulator (SOI) and other types of semiconductor material on insulator (SMOI) wafers are the subject of intense research and interest for next-generation technologies in the electronics industry. SMOI technology offers a host of benefits that are key enablers for next-generation technologies. SMOI wafers are useful for a large number of applications, such as:                high-bandwidth electronics, e.g., memory, high-speed processors and servers, video conferencing systems, direct cinema distribution and display, etc.;        low voltage, low power CMOS, e.g., portable computers, portable communications, notebooks, watches, PDAs, etc.;        high voltage and high power devices, e.g., automotive controls, power switches, display and audio power supplies, etc.; and        other applications, e.g., smart sensors and controls, MEMS, optoelectronics, radiation-hardened devices, smart power circuits and intrinsic gettering layers, among others.Depending on the semiconductor layer thickness and insulator thickness SMOI technology may be further sectioned into categories, such as, thin-body CMOS, fully-depleted CMOS, partially-depleted CMOS, bipolar power, etc. Currently, the International Technology Roadmap for Semiconductors (www.itrs.net) predicts the need to have thin-body CMOS (silicon layer thickness less than 10 nm) by about the year 2011.        
Moreover, SMOI substrates presently come in many different flavors, including, SOI with opaque substrate, germanium on insulator with opaque substrate, silicon on sapphire with transparent substrate and silicon-germanium on insulator with opaque substrate. The variants may be opaque or transparent to visible radiation. Some applications, such as backlit displays, micro-displays, head-mounted displays, etc., require transparent substrates for backlight to pass through. On the other hand, mainstream electronics usually utilize opaque substrates.
SMOI wafers need to have low surface roughness, low defect densities, low densities of pinholes in the insulator layer, high insulator breakdown field, low interface bubble density, low metallic contamination and low oxygen content in the semiconductor film layer. Furthermore, for more widespread industry acceptance, SMOI wafers need to significantly lower in cost and command only a small premium over conventional bulk silicon wafers. Unfortunately, most in-production SMOI techniques are too exotic and therefore too expensive to service the overall market segments where SMOI technology would otherwise be embraced.